The present invention relates to integrated circuits and in particular to complementary metal oxide semiconductor (CMOS) integrated circuit processes and devices.
Some CMOS integrated circuit processes have attempted to form transistor elements and one-time programmable elements, called xe2x80x9cpoly fuses,xe2x80x9d out of silicided polysilicon (also called polysilicide) on a polysilicon layer. These processes have tried to use the phenomenon of silicide xe2x80x9cagglomerationxe2x80x9d to program the poly fuses. When a sufficiently high current is dissipated in or passed through an unprogrammed poly fuse, the temperature of the fuse material (silicided polysilicon) rises above a certain critical temperature, which causes the silicided polysilicon to change phase. This phase change is commonly called xe2x80x9cagglomeration.xe2x80x9d The silicided polysilicon transitions from a low resistance phase to a high resistance phase, which is called xe2x80x9cprogrammingxe2x80x9d the fuse. In some cases, the phase change is accompanied by physical movement of the silicided polysilicon away from the hottest point, which can be ascertained by a post-processing physical analysis.
One-time programmable elements, such as silicide agglomeration fuses, may be used as programmable elements in a wide range of integrated circuit applications. In some applications, Moore""s law requires reduced supply voltages, which creates the desire for a high performance fuse that can be programmed at a low voltage.
A CMOS process with an integrated, high performance, silicide agglomeration fuse is provided in accordance with the present invention. The fuse structure in one embodiment of the invention provides optimum performance with low voltage programming. The CMOS process according to one embodiment of the invention may advantageously include all features or comply with all process conditions of a standard state-of-the-art 0.18 xcexcm or 0.13 xcexcm CMOS process or other CMOS processes. These conditions may include rapid thermal anneal (RTA) processes, temperatures and time periods for silicidation to form transistors. One embodiment of the proposed CMOS process of the invention includes an additional process to optimize the performance of a xe2x80x9cpoly fusexe2x80x9d programmable by polysilicide agglomeration.
One objective for a high performance, polysilicide agglomeration fuse is to have a post-programming fuse resistance (xe2x80x9cblown fusexe2x80x9d resistance) much higher than a pre-programming or unprogrammed fuse resistance (xe2x80x9cfresh fusexe2x80x9d resistance). The ratio of post-programming fuse resistance to pre-programming fuse resistance may be called the xe2x80x9cfigure of meritxe2x80x9d of the fuse. The poly fuse according to the present invention may increase this figure of merit by at least a factor of 10 to over 1000, for example. If the figure of merit of a poly fuse is sufficiently large, a sense circuit connected to the poly fuse may read the fuse after programming without any ambiguity.
If a programmed fuse with a very small xe2x80x9cfigure of meritxe2x80x9d value is read by the sense circuit as programmed, the fuse can cause circuit malfunction and reliability issues. If the sense circuit is designed to handle small values of the resistance ratio between a programmed and an unprogrammed fuse (figure of merit), the probability of circuit malfunction and unreliability is high. The improved fuse design of the present invention with a large figure of merit will greatly enhance circuit reliability and give greater flexibility for the designers to make robust sense circuit designs.
The process according to the invention forms a thinner field polysilicon layer (fuse poly) to ensure that the entire fuse poly layer is consumed during silicidation. When the thinner polysilicide is agglomerated during fuse programming, an insulator layer (e.g., TEOS or similar material) underneath the polysilicide is exposed, which forms an ideal open circuit. Thus, the post-programming resistance of this ideal polysilicide agglomeration fuse can be infinitely high.
One aspect of the invention relates to a method of forming an integrated circuit with a transistor and a polysilicide fuse. The method comprises forming a polysilicon layer on a surface of a silicon substrate, the silicon substrate having a first insulator and a second insulator formed at two areas on the surface of the silicon substrate; forming a mask layer over the polysilicon layer, the mask exposing an area of the polysilicon layer over the second insulator; and etching the exposed area of the polysilicon layer a pre-determined amount, such that an unetched portion of the polysilicon layer in the exposed area will react with a metal layer to form polysilicide during a rapid thermal anneal (RTA) process.
Another aspect of the invention relates to a complementary metal oxide semiconductor (CMOS) fabrication process. The process comprises creating a polysilicon layer having a first thickness for a transistor gate area and a second thickness for a fuse area, the first thickness being greater than the second thickness, wherein most of the polysilicon in the fuse area will react with a metal layer to form polysilicide during a rapid thermal anneal (RTA) process.
Another aspect of the invention relates to an integrated circuit. The circuit comprises a silicon substrate; a first insulator and a second insulator formed at two areas on a surface of the silicon substrate; a transistor formed on the silicon substrate between the first and second insulators; and a polysilicide fuse formed over the second insulator, the polysilicide fuse having an active area where polysilicide directly contacts the insulator, wherein the transistor and the polysilicide fuse are formed with a common silicidation process.